Technical search for semiconductors in Vietnam.
Vietnam's semiconductor industry is built on the back end. Intel's largest assembly and test site is in Ho Chi Minh City, and Amkor, Hana Micron and others have since added packaging and test capacity in the north. Design centres for global chip companies have grown alongside, mostly in verification, physical design and analog layout. The government has set a target of 50,000 semiconductor engineers by 2030, and the country's first front-end fab project — led by Viettel — is now underway. The engineers are real and increasingly experienced, but the field is young enough that one title can hide very different careers.
Semiconductors stratify more sharply than most industries, and the layer an employer sits in decides which decisions ever reach the people inside it. A fabless company owns the architecture, the product and the cost of being wrong in silicon. A foundry owns the process. An OSAT owns the package and the test floor as a service. A design service partner owns execution against a specification written by the customer. All four hire engineers with the same titles, and all four are hard to do well. That is why the clearest split is not seniority but whether the work was owned or executed. Two DFT leaders can each have run sixty engineers. One set the test strategy before tape-out, trading silicon area on compression against tester seconds that become cost of goods at volume, and lived with it when the part came back hard to test. The other ran scan insertion and pattern generation against a specification that arrived from elsewhere, on someone else's schedule, and did it well enough to keep winning the next project. Same title, same headcount, same vocabulary.
Vietnam now has engineers across every one of those roles — assembly and test, design services, captive design centres, and a domestic fabless industry just getting off the ground — so a shortlist can look uniform and actually come from four different worlds. Sometimes two centres under the same logo can be two different worlds — one owns the block end to end, the other just carries out decisions made in Santa Clara, Hsinchu or Seoul.
Roles we search for
Design
SoC architect · RTL design engineer · Analog design engineer · Mixed-signal design engineer · RF design engineer · High-speed and SerDes design engineer · Memory design engineer · Power management IC design engineer · IP integration engineer · Low power design engineer · IC design manager
Verification and DFT
Design verification engineer · Analog and mixed-signal verification engineer · Formal verification engineer · Emulation engineer · Post-silicon validation engineer · DFT engineer · Verification manager · DFT director
Physical design and signoff
Physical design engineer · Place and route engineer · Static timing analysis engineer · Analog layout engineer · Signal and power integrity engineer · Physical verification and signoff engineer · CAD and design methodology engineer
EDA and semiconductor IP
EDA R&D software engineer · EDA algorithm engineer · Corporate applications engineer · IP design engineer · IP verification engineer · Standard cell library engineer · PDK and design enablement engineer
Process and integration
Process integration engineer · Diffusion process engineer · Ion implant process engineer · Etch process engineer · Wet process and clean engineer · Thin film process engineer · Photolithography engineer · CMP process engineer · Device and TCAD engineer · Process development manager · Module owner
Packaging and assembly
Package design engineer · Packaging development engineer · Advanced packaging engineer · Substrate engineer · Assembly process engineer · Wire bond and die attach engineer · Flip chip process engineer · Molding and encapsulation engineer · Package thermal engineer · Package reliability engineer
Test engineering
Test engineering manager · ATE test engineer · Test development engineer · Load board and probe card engineer · Wafer sort and probe engineer · Burn-in engineer · Test floor operations manager
Yield, reliability and quality
Yield enhancement engineer · Failure analysis engineer · Product engineer · Characterization engineer · Reliability engineer · Reliability engineering manager · Process control and SPC engineer · Quality assurance manager · Supplier quality engineer · Customer quality engineer
Equipment and facilities
Equipment engineering manager · Process equipment engineer · Metrology engineer · Automation and MES engineer · Material handling automation engineer · Gas and chemical systems engineer · Facilities and cleanroom manager · EHS manager · Maintenance engineering lead
Operations and manufacturing
Manufacturing manager · Production engineering manager · Production planning manager · Industrial engineering lead · Manufacturing systems manager · Capacity planning manager · NPI manager · Shift operations manager
Applications and technical marketing
Field applications engineer · Technical marketing engineer · Product line manager · Customer programme manager
Leadership
Site director · ATP plant manager · Fab operations director · Engineering director · R&D director · Design centre director · Quality director
These searches start at a gross monthly package of around 50 million VND, or below that when several roles are open at once.
What we look at
Which layer of the value chain they actually worked in. Front-end fab, assembly and test, and design are three separate professions, and the same title appears in all of them. Within each, whether the work was theirs to own or theirs to execute against someone else's specification. For process and equipment roles: which node, on which toolsets, and whether they owned a module through a conversion or supported one. Yield and DPPM before and after their involvement, and whether the gain held. Which failure modes they diagnosed themselves, and with what — X-ray, C-SAM, cross-section. For packaging and assembly: which package types and which platforms, die attach, wire bond or flip chip, and what they changed when a lot came back failing. For test engineering: which ATE platforms, Advantest or Teradyne, and whether they cut test time without losing coverage. For design roles: how many tape-outs they completed, at which foundry and node, and what came back. For verification and DFT: how many blocks or full chips they closed, the coverage they had to reach and how they got the last few per cent, and whether they have debugged failing silicon. For physical design: block or full-chip, and whether they closed timing on the hard corners themselves. For EDA and IP: which tools they built or supported, and whether their IP shipped in someone else's product. For yield, reliability and quality: which customers audited them and how the findings were closed. For applications and technical marketing: which customers they supported, and whether a design win came out of it.
The deep pool here is in assembly, test and packaging, and increasingly in design verification and physical design. It is thin in front-end fab work — process integration, lithography, module ownership through a node transition — and in the leadership layer that runs a fab, roles Vietnam has so far filled with returnees and expatriates from Taiwan, Korea, Singapore and the US. That is beginning to change, but slowly, and a search at that level usually means going beyond Vietnam and waiting longer for the right person. We will tell you that on the first call rather than three months in.